\doxysubsubsection{PWR Exported Macro }
\hypertarget{group___p_w_r___exported___macro}{}\label{group___p_w_r___exported___macro}\index{PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga1ee778f7ff494723bd0ef04ec44b0f77}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+VOLTAGESCALING\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+REGULATOR\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Configure the main internal regulator output voltage. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga2977135bbea35b786805eea640d1c884}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+GET\+\_\+\+FLAG}}(\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Check PWR flags are set or not. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga8e3eb6bbc85beee17d213d64e99e8eed}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+GET\+\_\+\+WAKEUPFLAG}}(\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Check PWR wake up flags are set or not. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga96f24bf4b16c9f944cd829100bf746e5}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+CLEAR\+\_\+\+FLAG}}(\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Clear CPU PWR flags. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga21189c3a699027e3e932dff6985b2516}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+CLEAR\+\_\+\+WAKEUPFLAG}}(\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Clear PWR wake up flags. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga3180f039cf14ef78a64089f387f8f9c2}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT}}()
\begin{DoxyCompactList}\small\item\em Enable the PVD EXTI Line 16. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_gad240d7bf8f15191b068497b9aead1f1f}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT}}()
\begin{DoxyCompactList}\small\item\em Disable the PVD EXTI Line 16. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_gae5ba5672fe8cb7c1686c7f2cc211b128}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+EVENT}}()
\begin{DoxyCompactList}\small\item\em Enable event on PVD EXTI Line 16. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga8bd379e960497722450c7cea474a7e7a}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+EVENT}}()
\begin{DoxyCompactList}\small\item\em Disable event on PVD EXTI Line 16. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga7bef3f30c9fe267c99d5240fbf3f878c}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Enable the PVD Rising Interrupt Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga1ca8fd7f3286a176f6be540c75a004c6}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+RISING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Disable the PVD Rising Interrupt Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga5b971478563a00e1ee1a9d8ca8054e08}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+FALLING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Enable the PVD Falling Interrupt Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga1ca57168205f8cd8d1014e6eb9465f2d}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+FALLING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Disable the PVD Falling Interrupt Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga638033d236eb78c1e5ecb9b49c4e7f36}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+FALLING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Enable the PVD Rising \& Falling Interrupt Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga3f66c9c0c214cd08c24674904dcdc4e0}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+RISING\+\_\+\+FALLING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Disable the PVD Rising \& Falling Interrupt Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga5e66fa75359b51066e0731ac1e5ae438}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG}}()
\begin{DoxyCompactList}\small\item\em Check whether the specified PVD EXTI interrupt flag is set or not. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_gac0fb2218bc050f5d8fdb1a3f28590352}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG}}()
\begin{DoxyCompactList}\small\item\em Clear the PVD EXTI flag. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_gaba4a7968f5c4c4ca6a7047b147ba18d4}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+GENERATE\+\_\+\+SWIT}}()
\begin{DoxyCompactList}\small\item\em Generates a Software interrupt on PVD EXTI line. \end{DoxyCompactList}\end{DoxyCompactItemize}


\doxysubsubsubsection{Detailed Description}


\label{doc-define-members}
\Hypertarget{group___p_w_r___exported___macro_doc-define-members}
\doxysubsubsubsection{Macro Definition Documentation}
\Hypertarget{group___p_w_r___exported___macro_ga96f24bf4b16c9f944cd829100bf746e5}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_CLEAR\_FLAG@{\_\_HAL\_PWR\_CLEAR\_FLAG}}
\index{\_\_HAL\_PWR\_CLEAR\_FLAG@{\_\_HAL\_PWR\_CLEAR\_FLAG}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_CLEAR\_FLAG}{\_\_HAL\_PWR\_CLEAR\_FLAG}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_ga96f24bf4b16c9f944cd829100bf746e5} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+CLEAR\+\_\+\+FLAG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(PWR-\/>CPUCR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga852ddeb6ccda1c58d5674b856b122b17}{PWR\_CPUCR\_CSSF}})}

\end{DoxyCode}


Clear CPU PWR flags. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+FLAG\+\_\+\+\_\+} & \+: Specifies the flag to clear. \\
\hline
\end{DoxyParams}
\begin{DoxyNote}{Note}
This parameter is not used for the STM32\+H7 family and is kept as parameter just to maintain compatibility with other families. 

This macro clear all CPU flags. For single core devices except STM32\+H7\+Axxx and STM32\+H7\+Bxxx, CPU flags are STOPF, SBF, SBF\+\_\+\+D1 and SBF\+\_\+\+D2. For STM32\+H7\+Axxx and STM32\+H7\+Bxxx lines, CPU flags are STOPF and SBF. 
\end{DoxyNote}

\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_ga21189c3a699027e3e932dff6985b2516}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_CLEAR\_WAKEUPFLAG@{\_\_HAL\_PWR\_CLEAR\_WAKEUPFLAG}}
\index{\_\_HAL\_PWR\_CLEAR\_WAKEUPFLAG@{\_\_HAL\_PWR\_CLEAR\_WAKEUPFLAG}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_CLEAR\_WAKEUPFLAG}{\_\_HAL\_PWR\_CLEAR\_WAKEUPFLAG}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_ga21189c3a699027e3e932dff6985b2516} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+CLEAR\+\_\+\+WAKEUPFLAG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(PWR-\/>WKUPCR,\ (\_\_FLAG\_\_))}

\end{DoxyCode}


Clear PWR wake up flags. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+FLAG\+\_\+\+\_\+} & \+: Specifies the wake up flag to be cleared. This parameter can be one of the following values \+: \begin{DoxyItemize}
\item PWR\+\_\+\+FLAG\+\_\+\+WKUP1 \+: This parameter clear Wake up line 1 flag. \item PWR\+\_\+\+FLAG\+\_\+\+WKUP2 \+: This parameter clear Wake up line 2 flag. \item PWR\+\_\+\+FLAG\+\_\+\+WKUP3 \+: This parameter clear Wake up line 3 flag. \item PWR\+\_\+\+FLAG\+\_\+\+WKUP4 \+: This parameter clear Wake up line 4 flag. \item PWR\+\_\+\+FLAG\+\_\+\+WKUP5 \+: This parameter clear Wake up line 5 flag. \item PWR\+\_\+\+FLAG\+\_\+\+WKUP6 \+: This parameter clear Wake up line 6 flag. \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\begin{DoxyNote}{Note}
The PWR\+\_\+\+FLAG\+\_\+\+WKUP3 and PWR\+\_\+\+FLAG\+\_\+\+WKUP5 are available only for devices that support GPIOI port. 
\end{DoxyNote}

\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_ga2977135bbea35b786805eea640d1c884}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_GET\_FLAG@{\_\_HAL\_PWR\_GET\_FLAG}}
\index{\_\_HAL\_PWR\_GET\_FLAG@{\_\_HAL\_PWR\_GET\_FLAG}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_GET\_FLAG}{\_\_HAL\_PWR\_GET\_FLAG}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_ga2977135bbea35b786805eea640d1c884} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+GET\+\_\+\+FLAG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{(((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_PVDO)\ \ \ \ \ \ ?\ ((PWR-\/>CSR1\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf3e9a5812547f32576265e00802de3d0}{PWR\_CSR1\_PVDO}})\ \ \ \ \ \ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf3e9a5812547f32576265e00802de3d0}{PWR\_CSR1\_PVDO}})\ \ \ \ \ \ :\(\backslash\)}
\DoxyCodeLine{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_AVDO)\ \ \ \ \ \ ?\ ((PWR-\/>CSR1\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0839931d400544985c1955ed9eeb55e9}{PWR\_CSR1\_AVDO}})\ \ \ \ \ \ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0839931d400544985c1955ed9eeb55e9}{PWR\_CSR1\_AVDO}})\ \ \ \ \ \ :\(\backslash\)}
\DoxyCodeLine{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_ACTVOSRDY)\ ?\ ((PWR-\/>CSR1\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6c8845e351ae1b92d1e6ec45395102f3}{PWR\_CSR1\_ACTVOSRDY}})\ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6c8845e351ae1b92d1e6ec45395102f3}{PWR\_CSR1\_ACTVOSRDY}})\ :\(\backslash\)}
\DoxyCodeLine{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_BRR)\ \ \ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae3552758eb3c4985410fe8911560f298}{PWR\_CR2\_BRRDY}})\ \ \ \ \ \ \ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae3552758eb3c4985410fe8911560f298}{PWR\_CR2\_BRRDY}})\ \ \ \ \ \ :\(\backslash\)}
\DoxyCodeLine{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_VOSRDY)\ \ \ \ ?\ ((PWR-\/>SRDCR\ \&\ PWR\_SRDCR\_VOSRDY)\ \ ==\ PWR\_SRDCR\_VOSRDY)\ \ \ :\(\backslash\)}
\DoxyCodeLine{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SCUEN)\ \ \ \ \ ?\ ((PWR-\/>CR3\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf5a8423dbc59c5572057861d59115222}{PWR\_CR3\_SCUEN}})\ \ \ \ \ \ \ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf5a8423dbc59c5572057861d59115222}{PWR\_CR3\_SCUEN}})\ \ \ \ \ \ :\(\backslash\)}
\DoxyCodeLine{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_STOP)\ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3e53d09fb0c22170ff5b37f7587762ec}{PWR\_CPUCR\_STOPF}})\ \ \ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3e53d09fb0c22170ff5b37f7587762ec}{PWR\_CPUCR\_STOPF}})\ \ \ \ :\(\backslash\)}
\DoxyCodeLine{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SB)\ \ \ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4d4e251da597e8edc8374d3c7bf48c28}{PWR\_CPUCR\_SBF}})\ \ \ \ \ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4d4e251da597e8edc8374d3c7bf48c28}{PWR\_CPUCR\_SBF}})\ \ \ \ \ \ :\(\backslash\)}
\DoxyCodeLine{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_MMCVDO)\ \ \ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_MMCVDO)\ \ \ \ ==\ PWR\_CSR1\_MMCVDO)\ \ \ \ :\(\backslash\)}
\DoxyCodeLine{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_USB33RDY)\ \ ?\ ((PWR-\/>CR3\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga64e25571a035b217eee2f8d99f5ca20d}{PWR\_CR3\_USB33RDY}})\ \ \ \ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga64e25571a035b217eee2f8d99f5ca20d}{PWR\_CR3\_USB33RDY}})\ \ \ :\(\backslash\)}
\DoxyCodeLine{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_TEMPH)\ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab519388ffad6698f98ada73c4bf81248}{PWR\_CR2\_TEMPH}})\ \ \ \ \ \ \ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab519388ffad6698f98ada73c4bf81248}{PWR\_CR2\_TEMPH}})\ \ \ \ \ \ :\(\backslash\)}
\DoxyCodeLine{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_TEMPL)\ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga186c016996c65b07e913e83155082865}{PWR\_CR2\_TEMPL}})\ \ \ \ \ \ \ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga186c016996c65b07e913e83155082865}{PWR\_CR2\_TEMPL}})\ \ \ \ \ \ :\(\backslash\)}
\DoxyCodeLine{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_VBATH)\ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaac411ccef055ec95447cd8b736221e06}{PWR\_CR2\_VBATH}})\ \ \ \ \ \ \ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaac411ccef055ec95447cd8b736221e06}{PWR\_CR2\_VBATH}})\ \ \ \ \ \ :\(\backslash\)}
\DoxyCodeLine{\ ((PWR-\/>CR2\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga36dd5dc04502cb2bcfbbbad9247d47da}{PWR\_CR2\_VBATL}})\ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga36dd5dc04502cb2bcfbbbad9247d47da}{PWR\_CR2\_VBATL}}))}

\end{DoxyCode}


Check PWR flags are set or not. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+FLAG\+\_\+\+\_\+} & \+: Specifies the flag to check. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item PWR\+\_\+\+FLAG\+\_\+\+PVDO \+: PVD Output. This flag is valid only if PVD is enabled by the HAL\+\_\+\+PWR\+\_\+\+Enable\+PVD() function. The PVD is stopped by STANDBY mode. For this reason, this bit is equal to 0 after STANDBY or reset until the PVDE bit is set. \item PWR\+\_\+\+FLAG\+\_\+\+AVDO \+: AVD Output. This flag is valid only if AVD is enabled by the HAL\+\_\+\+PWREx\+\_\+\+Enable\+AVD() function. The AVD is stopped by STANDBY mode. For this reason, this bit is equal to 0 after STANDBY or reset until the AVDE bit is set. \item PWR\+\_\+\+FLAG\+\_\+\+ACTVOSRDY \+: This flag indicates that the Regulator voltage scaling output selection is ready. \item PWR\+\_\+\+FLAG\+\_\+\+BRR \+: Backup regulator ready flag. This bit is not reset when the device wakes up from STANDBY mode or by a system reset or power-\/on reset. \item PWR\+\_\+\+FLAG\+\_\+\+VOSRDY \+: This flag indicates that the Regulator voltage scaling output selection is ready. mode or by a system reset or power-\/on reset. \item PWR\+\_\+\+FLAG\+\_\+\+USB33\+RDY \+: This flag indicates that the USB supply from regulator is ready. \item PWR\+\_\+\+FLAG\+\_\+\+TEMPH \+: This flag indicates that the temperature equal or above high threshold level. \item PWR\+\_\+\+FLAG\+\_\+\+TEMPL \+: This flag indicates that the temperature equal or below low threshold level. \item PWR\+\_\+\+FLAG\+\_\+\+VBATH \+: This flag indicates that VBAT level equal or above high threshold level. \item PWR\+\_\+\+FLAG\+\_\+\+VBATL \+: This flag indicates that VBAT level equal or below low threshold level. \item PWR\+\_\+\+FLAG\+\_\+\+STOP \+: This flag indicates that the system entered in STOP mode. \item PWR\+\_\+\+FLAG\+\_\+\+SB \+: This flag indicates that the system entered in STANDBY mode. \item PWR\+\_\+\+FLAG\+\_\+\+SB\+\_\+\+D1 \+: This flag indicates that the D1 domain entered in STANDBY mode. \item PWR\+\_\+\+FLAG\+\_\+\+SB\+\_\+\+D2 \+: This flag indicates that the D2 domain entered in STANDBY mode. \item PWR\+\_\+\+FLAG2\+\_\+\+STOP \+: This flag indicates that the system entered in STOP mode. \item PWR\+\_\+\+FLAG2\+\_\+\+SB \+: This flag indicates that the system entered in STANDBY mode. \item PWR\+\_\+\+FLAG2\+\_\+\+SB\+\_\+\+D1 \+: This flag indicates that the D1 domain entered in STANDBY mode. \item PWR\+\_\+\+FLAG2\+\_\+\+SB\+\_\+\+D2 \+: This flag indicates that the D2 domain entered in STANDBY mode. \item PWR\+\_\+\+FLAG\+\_\+\+CPU\+\_\+\+HOLD \+: This flag indicates that the CPU1 wakes up with hold. \item PWR\+\_\+\+FLAG\+\_\+\+CPU2\+\_\+\+HOLD \+: This flag indicates that the CPU2 wakes up with hold. \item PWR\+\_\+\+FLAG\+\_\+\+SMPSEXTRDY \+: This flag indicates that the SMPS External supply is sready. \item PWR\+\_\+\+FLAG\+\_\+\+SCUEN \+: This flag indicates that the supply configuration update is enabled. \item PWR\+\_\+\+FLAG\+\_\+\+MMCVDO \+: This flag indicates that the VDDMMC is above or equal to 1.\+2 V. \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\begin{DoxyNote}{Note}
The PWR\+\_\+\+FLAG\+\_\+\+PVDO, PWR\+\_\+\+FLAG\+\_\+\+AVDO, PWR\+\_\+\+FLAG\+\_\+\+ACTVOSRDY, PWR\+\_\+\+FLAG\+\_\+\+BRR, PWR\+\_\+\+FLAG\+\_\+\+VOSRDY, PWR\+\_\+\+FLAG\+\_\+\+USB33\+RDY, PWR\+\_\+\+FLAG\+\_\+\+TEMPH, PWR\+\_\+\+FLAG\+\_\+\+TEMPL, PWR\+\_\+\+FLAG\+\_\+\+VBATH, PWR\+\_\+\+FLAG\+\_\+\+VBATL, PWR\+\_\+\+FLAG\+\_\+\+STOP and PWR\+\_\+\+FLAG\+\_\+\+SB flags are used for all H7 family lines. The PWR\+\_\+\+FLAG2\+\_\+\+STOP, PWR\+\_\+\+FLAG2\+\_\+\+SB, PWR\+\_\+\+FLAG2\+\_\+\+SB\+\_\+\+D1, PWR\+\_\+\+FLAG2\+\_\+\+SB\+\_\+\+D2, PWR\+\_\+\+FLAG\+\_\+\+CPU\+\_\+\+HOLD and PWR\+\_\+\+FLAG\+\_\+\+CPU2\+\_\+\+HOLD flags are used only for H7 dual core lines. The PWR\+\_\+\+FLAG\+\_\+\+SB\+\_\+\+D1 and PWR\+\_\+\+FLAG\+\_\+\+SB\+\_\+\+D2 flags are used for all H7 family except STM32\+H7\+Axxx and STM32\+H7\+Bxxx lines. The PWR\+\_\+\+FLAG\+\_\+\+MMCVDO flag is used only for STM32\+H7\+Axxx and STM32\+H7\+Bxxx lines. The PWR\+\_\+\+FLAG\+\_\+\+SCUEN flag is used for devices that support only LDO regulator. The PWR\+\_\+\+FLAG\+\_\+\+SMPSEXTRDY flag is used for devices that support LDO and SMPS regulators. 
\end{DoxyNote}

\begin{DoxyRetVals}{Return values}
{\em The} & ({\bfseries{FLAG}}) state (TRUE or FALSE). \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_ga8e3eb6bbc85beee17d213d64e99e8eed}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_GET\_WAKEUPFLAG@{\_\_HAL\_PWR\_GET\_WAKEUPFLAG}}
\index{\_\_HAL\_PWR\_GET\_WAKEUPFLAG@{\_\_HAL\_PWR\_GET\_WAKEUPFLAG}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_GET\_WAKEUPFLAG}{\_\_HAL\_PWR\_GET\_WAKEUPFLAG}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_ga8e3eb6bbc85beee17d213d64e99e8eed} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+GET\+\_\+\+WAKEUPFLAG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((PWR-\/>WKUPFR\ \&\ (\_\_FLAG\_\_))\ ?\ 0\ :\ 1)}

\end{DoxyCode}


Check PWR wake up flags are set or not. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+FLAG\+\_\+\+\_\+} & specifies the wake up flag to check. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item PWR\+\_\+\+FLAG\+\_\+\+WKUP1 \+: This parameter clear Wake up line 1 flag. \item PWR\+\_\+\+FLAG\+\_\+\+WKUP2 \+: This parameter clear Wake up line 2 flag. \item PWR\+\_\+\+FLAG\+\_\+\+WKUP3 \+: This parameter clear Wake up line 3 flag. \item PWR\+\_\+\+FLAG\+\_\+\+WKUP4 \+: This parameter clear Wake up line 4 flag. \item PWR\+\_\+\+FLAG\+\_\+\+WKUP5 \+: This parameter clear Wake up line 5 flag. \item PWR\+\_\+\+FLAG\+\_\+\+WKUP6 \+: This parameter clear Wake up line 6 flag. \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\begin{DoxyNote}{Note}
The PWR\+\_\+\+FLAG\+\_\+\+WKUP3 and PWR\+\_\+\+FLAG\+\_\+\+WKUP5 are available only for devices that support GPIOI port. 
\end{DoxyNote}

\begin{DoxyRetVals}{Return values}
{\em The} & ({\bfseries{FLAG}}) state (TRUE or FALSE). \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_gac0fb2218bc050f5d8fdb1a3f28590352}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_PVD\_EXTI\_CLEAR\_FLAG@{\_\_HAL\_PWR\_PVD\_EXTI\_CLEAR\_FLAG}}
\index{\_\_HAL\_PWR\_PVD\_EXTI\_CLEAR\_FLAG@{\_\_HAL\_PWR\_PVD\_EXTI\_CLEAR\_FLAG}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_PVD\_EXTI\_CLEAR\_FLAG}{\_\_HAL\_PWR\_PVD\_EXTI\_CLEAR\_FLAG}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_gac0fb2218bc050f5d8fdb1a3f28590352} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(EXTI-\/>PR1,\ \mbox{\hyperlink{group___p_w_r___p_v_d___e_x_t_i___line_ga43a49255649e03d2d2b6b12c5c379d2b}{PWR\_EXTI\_LINE\_PVD}})}

\end{DoxyCode}


Clear the PVD EXTI flag. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_ga8bd379e960497722450c7cea474a7e7a}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_EVENT@{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_EVENT}}
\index{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_EVENT@{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_EVENT}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_EVENT}{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_EVENT}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_ga8bd379e960497722450c7cea474a7e7a} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+EVENT(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{CLEAR\_BIT(EXTI-\/>EMR1,\ \mbox{\hyperlink{group___p_w_r___p_v_d___e_x_t_i___line_ga43a49255649e03d2d2b6b12c5c379d2b}{PWR\_EXTI\_LINE\_PVD}})}

\end{DoxyCode}


Disable event on PVD EXTI Line 16. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_ga1ca57168205f8cd8d1014e6eb9465f2d}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_FALLING\_EDGE@{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_FALLING\_EDGE}}
\index{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_FALLING\_EDGE@{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_FALLING\_EDGE}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_FALLING\_EDGE}{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_FALLING\_EDGE}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_ga1ca57168205f8cd8d1014e6eb9465f2d} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+FALLING\+\_\+\+EDGE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{CLEAR\_BIT(EXTI-\/>FTSR1,\ \mbox{\hyperlink{group___p_w_r___p_v_d___e_x_t_i___line_ga43a49255649e03d2d2b6b12c5c379d2b}{PWR\_EXTI\_LINE\_PVD}})}

\end{DoxyCode}


Disable the PVD Falling Interrupt Trigger. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_gad240d7bf8f15191b068497b9aead1f1f}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_IT@{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_IT}}
\index{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_IT@{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_IT}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_IT}{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_IT}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_gad240d7bf8f15191b068497b9aead1f1f} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{CLEAR\_BIT(EXTI-\/>IMR1,\ \mbox{\hyperlink{group___p_w_r___p_v_d___e_x_t_i___line_ga43a49255649e03d2d2b6b12c5c379d2b}{PWR\_EXTI\_LINE\_PVD}})}

\end{DoxyCode}


Disable the PVD EXTI Line 16. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_ga1ca8fd7f3286a176f6be540c75a004c6}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_EDGE@{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_EDGE}}
\index{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_EDGE@{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_EDGE}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_EDGE}{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_EDGE}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_ga1ca8fd7f3286a176f6be540c75a004c6} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+RISING\+\_\+\+EDGE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{CLEAR\_BIT(EXTI-\/>RTSR1,\ \mbox{\hyperlink{group___p_w_r___p_v_d___e_x_t_i___line_ga43a49255649e03d2d2b6b12c5c379d2b}{PWR\_EXTI\_LINE\_PVD}})}

\end{DoxyCode}


Disable the PVD Rising Interrupt Trigger. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_ga3f66c9c0c214cd08c24674904dcdc4e0}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_FALLING\_EDGE@{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_FALLING\_EDGE}}
\index{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_FALLING\_EDGE@{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_FALLING\_EDGE}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_FALLING\_EDGE}{\_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_FALLING\_EDGE}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_ga3f66c9c0c214cd08c24674904dcdc4e0} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+RISING\+\_\+\+FALLING\+\_\+\+EDGE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\textcolor{keywordflow}{do}\ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_EDGE();\ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_FALLING\_EDGE();\ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\}\ \textcolor{keywordflow}{while}(0);}

\end{DoxyCode}


Disable the PVD Rising \& Falling Interrupt Trigger. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_gae5ba5672fe8cb7c1686c7f2cc211b128}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_EVENT@{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_EVENT}}
\index{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_EVENT@{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_EVENT}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_EVENT}{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_EVENT}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_gae5ba5672fe8cb7c1686c7f2cc211b128} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+EVENT(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(EXTI-\/>EMR1,\ \mbox{\hyperlink{group___p_w_r___p_v_d___e_x_t_i___line_ga43a49255649e03d2d2b6b12c5c379d2b}{PWR\_EXTI\_LINE\_PVD}})}

\end{DoxyCode}


Enable event on PVD EXTI Line 16. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_ga5b971478563a00e1ee1a9d8ca8054e08}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_FALLING\_EDGE@{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_FALLING\_EDGE}}
\index{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_FALLING\_EDGE@{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_FALLING\_EDGE}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_FALLING\_EDGE}{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_FALLING\_EDGE}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_ga5b971478563a00e1ee1a9d8ca8054e08} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+FALLING\+\_\+\+EDGE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(EXTI-\/>FTSR1,\ \mbox{\hyperlink{group___p_w_r___p_v_d___e_x_t_i___line_ga43a49255649e03d2d2b6b12c5c379d2b}{PWR\_EXTI\_LINE\_PVD}})}

\end{DoxyCode}


Enable the PVD Falling Interrupt Trigger. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_ga3180f039cf14ef78a64089f387f8f9c2}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_IT@{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_IT}}
\index{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_IT@{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_IT}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_IT}{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_IT}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_ga3180f039cf14ef78a64089f387f8f9c2} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(EXTI-\/>IMR1,\ \mbox{\hyperlink{group___p_w_r___p_v_d___e_x_t_i___line_ga43a49255649e03d2d2b6b12c5c379d2b}{PWR\_EXTI\_LINE\_PVD}})}

\end{DoxyCode}


Enable the PVD EXTI Line 16. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_ga7bef3f30c9fe267c99d5240fbf3f878c}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_EDGE@{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_EDGE}}
\index{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_EDGE@{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_EDGE}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_EDGE}{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_EDGE}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_ga7bef3f30c9fe267c99d5240fbf3f878c} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+EDGE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(EXTI-\/>RTSR1,\ \mbox{\hyperlink{group___p_w_r___p_v_d___e_x_t_i___line_ga43a49255649e03d2d2b6b12c5c379d2b}{PWR\_EXTI\_LINE\_PVD}})}

\end{DoxyCode}


Enable the PVD Rising Interrupt Trigger. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_ga638033d236eb78c1e5ecb9b49c4e7f36}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_FALLING\_EDGE@{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_FALLING\_EDGE}}
\index{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_FALLING\_EDGE@{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_FALLING\_EDGE}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_FALLING\_EDGE}{\_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_FALLING\_EDGE}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_ga638033d236eb78c1e5ecb9b49c4e7f36} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+FALLING\+\_\+\+EDGE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\textcolor{keywordflow}{do}\ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_EDGE();\ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_FALLING\_EDGE();\ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\}\ \textcolor{keywordflow}{while}(0);}

\end{DoxyCode}


Enable the PVD Rising \& Falling Interrupt Trigger. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_gaba4a7968f5c4c4ca6a7047b147ba18d4}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_PVD\_EXTI\_GENERATE\_SWIT@{\_\_HAL\_PWR\_PVD\_EXTI\_GENERATE\_SWIT}}
\index{\_\_HAL\_PWR\_PVD\_EXTI\_GENERATE\_SWIT@{\_\_HAL\_PWR\_PVD\_EXTI\_GENERATE\_SWIT}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_PVD\_EXTI\_GENERATE\_SWIT}{\_\_HAL\_PWR\_PVD\_EXTI\_GENERATE\_SWIT}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_gaba4a7968f5c4c4ca6a7047b147ba18d4} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+GENERATE\+\_\+\+SWIT(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(EXTI-\/>SWIER1,\ \mbox{\hyperlink{group___p_w_r___p_v_d___e_x_t_i___line_ga43a49255649e03d2d2b6b12c5c379d2b}{PWR\_EXTI\_LINE\_PVD}})}

\end{DoxyCode}


Generates a Software interrupt on PVD EXTI line. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_ga5e66fa75359b51066e0731ac1e5ae438}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_PVD\_EXTI\_GET\_FLAG@{\_\_HAL\_PWR\_PVD\_EXTI\_GET\_FLAG}}
\index{\_\_HAL\_PWR\_PVD\_EXTI\_GET\_FLAG@{\_\_HAL\_PWR\_PVD\_EXTI\_GET\_FLAG}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_PVD\_EXTI\_GET\_FLAG}{\_\_HAL\_PWR\_PVD\_EXTI\_GET\_FLAG}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_ga5e66fa75359b51066e0731ac1e5ae438} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((READ\_BIT(EXTI-\/>PR1,\ \mbox{\hyperlink{group___p_w_r___p_v_d___e_x_t_i___line_ga43a49255649e03d2d2b6b12c5c379d2b}{PWR\_EXTI\_LINE\_PVD}})\ ==\ \mbox{\hyperlink{group___p_w_r___p_v_d___e_x_t_i___line_ga43a49255649e03d2d2b6b12c5c379d2b}{PWR\_EXTI\_LINE\_PVD}})\ ?\ 1UL\ :\ 0UL)}

\end{DoxyCode}


Check whether the specified PVD EXTI interrupt flag is set or not. 


\begin{DoxyRetVals}{Return values}
{\em EXTI} & PVD Line Status. \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___p_w_r___exported___macro_ga1ee778f7ff494723bd0ef04ec44b0f77}\index{PWR Exported Macro@{PWR Exported Macro}!\_\_HAL\_PWR\_VOLTAGESCALING\_CONFIG@{\_\_HAL\_PWR\_VOLTAGESCALING\_CONFIG}}
\index{\_\_HAL\_PWR\_VOLTAGESCALING\_CONFIG@{\_\_HAL\_PWR\_VOLTAGESCALING\_CONFIG}!PWR Exported Macro@{PWR Exported Macro}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_PWR\_VOLTAGESCALING\_CONFIG}{\_\_HAL\_PWR\_VOLTAGESCALING\_CONFIG}}
{\footnotesize\ttfamily \label{group___p_w_r___exported___macro_ga1ee778f7ff494723bd0ef04ec44b0f77} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+VOLTAGESCALING\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+REGULATOR\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\textcolor{keywordflow}{do}\ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ tmpreg\ =\ 0x00;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \textcolor{comment}{/*\ Configure\ the\ Voltage\ Scaling\ */}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ MODIFY\_REG\ (PWR-\/>D3CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5566cb64c9ef928873024d23f3721050}{PWR\_D3CR\_VOS}},\ (\_\_REGULATOR\_\_));\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \textcolor{comment}{/*\ Delay\ after\ setting\ the\ voltage\ scaling\ */}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ tmpreg\ =\ READ\_BIT(PWR-\/>D3CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5566cb64c9ef928873024d23f3721050}{PWR\_D3CR\_VOS}});\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ UNUSED(tmpreg);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\}\ \textcolor{keywordflow}{while}(0)}

\end{DoxyCode}


Configure the main internal regulator output voltage. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+REGULATOR\+\_\+\+\_\+} & \+: Specifies the regulator output voltage to achieve a trade-\/off between performance and power consumption when the device does not operate at the maximum frequency (refer to the datasheet for more details). This parameter can be one of the following values\+: \begin{DoxyItemize}
\item PWR\+\_\+\+REGULATOR\+\_\+\+VOLTAGE\+\_\+\+SCALE0 \+: Regulator voltage output Scale 0 mode. \item PWR\+\_\+\+REGULATOR\+\_\+\+VOLTAGE\+\_\+\+SCALE1 \+: Regulator voltage output Scale 1 mode. \item PWR\+\_\+\+REGULATOR\+\_\+\+VOLTAGE\+\_\+\+SCALE2 \+: Regulator voltage output Scale 2 mode. \item PWR\+\_\+\+REGULATOR\+\_\+\+VOLTAGE\+\_\+\+SCALE3 \+: Regulator voltage output Scale 3 mode. \end{DoxyItemize}
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\hline
\end{DoxyParams}
\begin{DoxyNote}{Note}
For STM32\+H74x and STM32\+H75x lines, configuring Voltage Scale 0 is only possible when Vcore is supplied from LDO (Low Drop\+Out). The SYSCFG Clock must be enabled through \doxylink{group___r_c_c___exported___macros_gafc3ffcbb86e4913ae336ba094ca199e1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+CLK\+\_\+\+ENABLE()} macro before configuring Voltage Scale 0 using \doxylink{group___p_w_r___exported___macro_ga1ee778f7ff494723bd0ef04ec44b0f77}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+VOLTAGESCALING\+\_\+\+CONFIG()}. Transition to Voltage Scale 0 is only possible when the system is already in Voltage Scale 1. Transition from Voltage Scale 0 is only possible to Voltage Scale 1 then once in Voltage Scale 1 it is possible to switch to another voltage scale. After each regulator voltage setting, wait on VOSRDY flag to be set using macro \doxylink{group___p_w_r___exported___macro_ga2977135bbea35b786805eea640d1c884}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+GET\+\_\+\+FLAG()}. To enter low power mode , and if current regulator voltage is Voltage Scale 0 then first switch to Voltage Scale 1 before entering low power mode. 
\end{DoxyNote}

\begin{DoxyRetVals}{Return values}
{\em None.} & \\
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\end{DoxyRetVals}
